US 11,876,516 B2
Non-fighting level shifters
Peter Kwang Lee, Pleasanton, CA (US); Kapil Dev Dwivedi, Mirzapur (IN); and John Edward Barth, Williston, VT (US)
Assigned to Synopsys, Inc., Sunnyvale, CA (US)
Filed by Synopsys, Inc., Mountain View, CA (US)
Filed on Nov. 12, 2021, as Appl. No. 17/525,345.
Claims priority of provisional application 63/113,489, filed on Nov. 13, 2020.
Prior Publication US 2022/0158638 A1, May 19, 2022
Int. Cl. H03K 19/0185 (2006.01); H03K 3/037 (2006.01)
CPC H03K 19/018521 (2013.01) [H03K 3/037 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A level shifter circuit, comprising:
a first current mirror coupled between a power terminal and a ground terminal, wherein the first current mirror comprises a first n-type transistor gated by an input signal, and wherein the first current mirror is self-timed;
a second current mirror coupled between the power terminal and the ground terminal, wherein the second current mirror comprises a second n-type transistor gated by an inverse of the input signal, and wherein the second current mirror is self-timed;
a level shifter, wherein the level shifter includes a first transistor coupled to the first current mirror and a second transistor coupled to the second current mirror, wherein the first current mirror and the second current mirror control a state of the first transistor and the second transistor;
a first shoot-thru current section comprising a first inverter and a second inverter directly coupled between a gate of the first transistor and the first current mirror; and
a second shoot-thru current section comprising a third inverter and a fourth inverter directly coupled between a gate of the second transistor and the second current mirror.