CPC H03F 1/3247 (2013.01) [H04B 17/12 (2015.01); H04B 17/14 (2015.01); H04B 17/24 (2015.01)] | 16 Claims |
9. A device comprising:
a receiver configured to sample a signal having a pattern of alternating amplitude steps separated by a silence gap length, wherein the receiver is configured to provide a sample signal, wherein the pattern of alternating amplitude steps includes a first set of steps that increase in amplitude over time interleaved with a second set of steps that decrease in amplitude over time;
an accumulator coupled to the receiver and configured to receive the sample signal and determine an accumulated sample signal for each of the amplitude steps; and
a processor coupled to the accumulator, wherein the processor is configured to execute instructions stored on a non-transitory computer readable storage medium that when executed cause the processor to:
determine a first value and a second value for the accumulated sample signal for each of the amplitude steps; and
determine a correction value based on the first value and the second value for the accumulated sample signal for each of the amplitude steps.
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