US 11,876,121 B2
Self-aligned gate endcap (SAGE) architecture having gate or contact plugs
Sairam Subramanian, Portland, OR (US); and Walid M. Hafez, Portland, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Jul. 22, 2022, as Appl. No. 17/871,693.
Application 17/871,693 is a continuation of application No. 16/294,307, filed on Mar. 6, 2019, granted, now 11,444,171.
Prior Publication US 2022/0359705 A1, Nov. 10, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 29/49 (2006.01); H01L 27/088 (2006.01); H01L 23/535 (2006.01); H01L 21/8234 (2006.01)
CPC H01L 29/4983 (2013.01) [H01L 21/823431 (2013.01); H01L 21/823437 (2013.01); H01L 21/823481 (2013.01); H01L 23/535 (2013.01); H01L 27/0886 (2013.01)] 24 Claims
OG exemplary drawing
 
1. An integrated circuit structure, comprising:
a first gate structure over and surrounding a channel region of a first nanowire;
a second gate structure over and surrounding a channel region of a second nanowire;
a gate endcap isolation structure between the first and second nanowires and laterally between and in contact with the first and second gate structures;
a gate plug over the gate endcap isolation structure and laterally between the first gate structure and the second gate structure; and
a crystalline metal oxide material laterally between and in contact with the gate plug and the first gate structure, and laterally between and in contact with the gate plug and the second gate structure.