| CPC H01L 27/0928 (2013.01) [H01L 29/0673 (2013.01); H01L 29/1033 (2013.01); H01L 29/42356 (2013.01); H01L 29/42392 (2013.01); H01L 29/7854 (2013.01)] | 20 Claims |
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1. A semiconductor device, comprising:
a first active fin and a second active fin protruding from a substrate in a vertical direction perpendicular to an upper surface of the substrate, the first active fin and the second active fin extending in a first direction perpendicular to the vertical direction;
a plurality of first channel layers vertically stacked on the first active fin to be spaced apart from each other in the vertical direction, the plurality of first channel layers having first side surfaces and second side surfaces, the second side surfaces opposing the first side surfaces in a second direction perpendicular to each of the first direction and the vertical direction;
a plurality of second channel layers vertically stacked on the second active fin to be spaced apart from each other in the vertical direction, the plurality of second channel layers having third side surfaces and fourth side surfaces, the fourth side surfaces opposing the third side surfaces in the second direction;
a first source/drain layer on the first active fin to be in contact with the plurality of first channel layers;
a second source/drain layer on the second active fin to be in contact with the plurality of second channel layers;
a first gate electrode extending in the second direction and surrounding the plurality of first channel layers and the plurality of second channel layers, the first gate electrode having a first end portion and a second end portion opposing each other in the second direction, and the first gate electrode having a center portion at a substantially same distance from each of the first end portion and the second end portion between the first end portion and the second end portion in the second direction;
an interlayer dielectric layer on the first source/drain layer and the second source/drain layer; and
gate isolation patterns respectively adjacent to the first end portion and the second end portion of the first gate electrode,
wherein a first distance from the first end portion of the first gate electrode to the first side surfaces of the plurality of first channel layers in the second direction is shorter than a second distance from the center portion of the first gate electrode to the second side surfaces of the plurality of first channel layers in the second direction, and
wherein a third distance from the second end portion of the first gate electrode to the third side surfaces of the plurality of second channel layers in the second direction is shorter than a fourth distance from the center portion of the first gate electrode to the fourth side surfaces of the plurality of second channel layers in the second direction.
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