US 11,876,089 B2
Electrostatic discharge (ESD) protection for CMOS circuits
Shih-Fan Chen, Hsinchu (TW); and Abhijat Goyal, Lakeway, TX (US)
Assigned to Synaptics Incorporated, San Jose, CA (US)
Filed by Synaptics Incorporated, San Jose, CA (US)
Filed on Feb. 12, 2021, as Appl. No. 17/175,168.
Claims priority of provisional application 62/976,635, filed on Feb. 14, 2020.
Prior Publication US 2021/0257353 A1, Aug. 19, 2021
Int. Cl. H01L 27/02 (2006.01); H02H 9/04 (2006.01)
CPC H01L 27/0285 (2013.01) [H02H 9/046 (2013.01)] 13 Claims
OG exemplary drawing
 
1. A voltage clamp, comprising:
a first transistor having a drain coupled to a power supply;
a second transistor having a drain coupled to a source of the first transistor and a source coupled to ground;
a third transistor configured to produce a positive feedback signal based on a first voltage at a gate of the second transistor;
a first inverter configured to control an operation of the first transistor based at least in part on the positive feedback signal so that the first transistor and the second transistor provide a discharge path between the power supply and ground;
a second inverter configured to produce the first voltage at the gate of the second transistor;
a voltage divider coupled between the power supply and ground and configured to provide a voltage divider output signal to an input of the second inverter; and
a first resistor-capacitor (RC) network coupled between the voltage divider and the second inverter, the first RC network being configured to filter the voltage divider output signal provided to the input of the second inverter.