US 11,876,079 B2
Method for fabricating semiconductor device with recessed pad layer
Shing-Yih Shih, New Taipei (TW)
Assigned to NANYA TECHNOLOGY CORPORATION, New Taipei (TW)
Filed by NANYA TECHNOLOGY CORPORATION, New Taipei (TW)
Filed on Nov. 24, 2021, as Appl. No. 17/534,836.
Application 17/534,836 is a division of application No. 16/945,096, filed on Jul. 31, 2020, granted, now 11,329,028.
Prior Publication US 2022/0084987 A1, Mar. 17, 2022
Int. Cl. H01L 25/065 (2023.01); H01L 21/768 (2006.01); H01L 23/00 (2006.01); H01L 23/48 (2006.01); H01L 25/00 (2006.01)
CPC H01L 25/0657 (2013.01) [H01L 21/76898 (2013.01); H01L 23/481 (2013.01); H01L 24/08 (2013.01); H01L 24/80 (2013.01); H01L 25/50 (2013.01); H01L 2224/08145 (2013.01); H01L 2224/80895 (2013.01); H01L 2224/80896 (2013.01); H01L 2225/06541 (2013.01)] 15 Claims
OG exemplary drawing
 
1. A method for fabricating a semiconductor device, comprising:
performing a bonding process to bond a second die onto a first die comprising a pad layer;
forming a through-substrate opening along the second die and extending to the pad layer in the first die;
conformally forming an isolation layer in the through-substrate opening;
performing a punch etch process to remove a portion of the isolation layer and expose a portion of a top surface of the pad layer;
performing an isotropic etch process to form a recessed space extending from the through substrate opening and in the pad layer;
conformally forming a barrier layer in the through-substrate opening and the recessed space; and
forming a filler layer in the through-substrate opening and the recessed space.