US 11,876,073 B2
Process for collectively fabricating a plurality of semiconductor structures
David Sotta, Grenoble (FR)
Assigned to SOITEC, Bernin (FR)
Appl. No. 17/291,957
Filed by Soitec, Bernin (FR)
PCT Filed Oct. 24, 2019, PCT No. PCT/FR2019/052538
§ 371(c)(1), (2) Date May 6, 2021,
PCT Pub. No. WO2020/094944, PCT Pub. Date May 14, 2020.
Claims priority of application No. 1860294 (FR), filed on Nov. 8, 2018.
Prior Publication US 2022/0005785 A1, Jan. 6, 2022
Int. Cl. H01L 21/02 (2006.01); H01L 23/00 (2006.01); H01L 33/00 (2010.01); H01L 21/20 (2006.01); H01L 25/065 (2023.01); H01L 25/00 (2006.01)
CPC H01L 24/94 (2013.01) [H01L 21/02639 (2013.01); H01L 21/2007 (2013.01); H01L 25/0655 (2013.01); H01L 25/50 (2013.01); H01L 33/0093 (2020.05); H01L 2224/94 (2013.01)] 18 Claims
OG exemplary drawing
 
1. A method of collectively fabricating a plurality of semiconductor structures, comprising:
providing a substrate including a carrier having a main face, a dielectric layer on the main face of the carrier and a plurality of crystalline semiconductor growth islands on the dielectric layer;
forming a crystalline semiconductor active layer on the plurality of crystalline semiconductor growth islands; and
after the step of forming the crystalline semiconductor active layer, forming trenches in the crystalline semiconductor active layer and the plurality of crystalline semiconductor growth islands in order to define the plurality of semiconductor structures.