US 11,876,056 B2
Silicon nitride metal layer covers
Jonathan Andrew Montoya, Dallas, TX (US); and Salvatore Franks Pavone, Murphy, TX (US)
Assigned to TEXAS INSTRUMENTS INCORPORATED, Dallas, TX (US)
Filed by TEXAS INSTRUMENTS INCORPORATED, Dallas, TX (US)
Filed on Apr. 30, 2021, as Appl. No. 17/246,561.
Prior Publication US 2022/0352098 A1, Nov. 3, 2022
Int. Cl. H01L 23/00 (2006.01)
CPC H01L 23/564 (2013.01) [H01L 24/03 (2013.01); H01L 24/05 (2013.01); H01L 24/13 (2013.01); H01L 2224/0346 (2013.01); H01L 2224/0391 (2013.01); H01L 2224/0401 (2013.01); H01L 2224/05024 (2013.01); H01L 2224/13026 (2013.01); H01L 2924/05042 (2013.01); H01L 2924/07025 (2013.01)] 15 Claims
OG exemplary drawing
 
1. A semiconductor package, comprising:
a semiconductor die;
a passivation layer abutting a device side of the semiconductor die;
a first conductive layer abutting the device side of the semiconductor die;
a second conductive layer the passivation layer and physically contacting the first conductive layer;
a silicon nitride layer abutting the second conductive layer; and
a third conductive layer coupled to the second conductive layer at a gap in the silicon nitride layer, the third conductive layer configured to receive a solder ball.