US 11,876,053 B2
Multi-chip package and method of providing die-to-die interconnects in same
Henning Braunisch, Chandler, AZ (US); Chia-Pin Chiu, Tempe, AZ (US); Aleksandar Aleksov, Chandler, AZ (US); Hinmeng Au, Phoenix, AZ (US); Stefanie M. Lotz, Phoenix, AZ (US); Johanna M. Swan, Scottsdale, AZ (US); and Sujit Sharan, Chandler, AZ (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Jan. 7, 2021, as Appl. No. 17/144,130.
Application 16/677,533 is a division of application No. 15/876,080, filed on Jan. 19, 2018, granted, now 10,510,669, issued on Dec. 17, 2019.
Application 15/876,080 is a division of application No. 13/531,827, filed on Jun. 25, 2012, granted, now 9,875,969, issued on Jan. 23, 2018.
Application 13/531,827 is a division of application No. 12/459,007, filed on Jun. 24, 2009, granted, now 8,227,904, issued on Jul. 24, 2012.
Application 17/144,130 is a continuation of application No. 16/940,024, filed on Jul. 27, 2020, granted, now 10,923,429.
Application 16/940,024 is a continuation of application No. 16/677,533, filed on Nov. 7, 2019, granted, now 10,763,216, issued on Sep. 1, 2020.
Prior Publication US 2021/0134726 A1, May 6, 2021
Int. Cl. H01L 23/538 (2006.01); H01L 23/13 (2006.01); H01L 23/00 (2006.01); H01L 25/065 (2023.01); H01L 21/683 (2006.01)
CPC H01L 23/5385 (2013.01) [H01L 23/13 (2013.01); H01L 23/5381 (2013.01); H01L 24/14 (2013.01); H01L 24/73 (2013.01); H01L 25/0652 (2013.01); H01L 25/0655 (2013.01); H01L 25/0657 (2013.01); H01L 21/6835 (2013.01); H01L 24/17 (2013.01); H01L 24/45 (2013.01); H01L 24/48 (2013.01); H01L 24/49 (2013.01); H01L 24/81 (2013.01); H01L 2224/0401 (2013.01); H01L 2224/13099 (2013.01); H01L 2224/141 (2013.01); H01L 2224/1403 (2013.01); H01L 2224/16145 (2013.01); H01L 2224/16225 (2013.01); H01L 2224/17181 (2013.01); H01L 2224/32245 (2013.01); H01L 2224/45099 (2013.01); H01L 2224/45147 (2013.01); H01L 2224/48091 (2013.01); H01L 2224/48227 (2013.01); H01L 2224/49175 (2013.01); H01L 2224/73207 (2013.01); H01L 2224/73253 (2013.01); H01L 2224/81001 (2013.01); H01L 2224/81005 (2013.01); H01L 2224/81801 (2013.01); H01L 2225/0651 (2013.01); H01L 2225/06513 (2013.01); H01L 2225/06517 (2013.01); H01L 2225/06562 (2013.01); H01L 2924/00011 (2013.01); H01L 2924/00014 (2013.01); H01L 2924/014 (2013.01); H01L 2924/01005 (2013.01); H01L 2924/01006 (2013.01); H01L 2924/01015 (2013.01); H01L 2924/01029 (2013.01); H01L 2924/01032 (2013.01); H01L 2924/01033 (2013.01); H01L 2924/01076 (2013.01); H01L 2924/01079 (2013.01); H01L 2924/10253 (2013.01); H01L 2924/10271 (2013.01); H01L 2924/10329 (2013.01); H01L 2924/12042 (2013.01); H01L 2924/1461 (2013.01); H01L 2924/15153 (2013.01); H01L 2924/19107 (2013.01); H01L 2924/351 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A multi-chip package comprising:
a substrate having a first side, an opposing second side, and a third side that extends from the first side to the second side, the third side constituting a portion of an outside perimeter of the substrate;
a first die attached to the first side of the substrate;
a second die attached to the first side of the substrate; and
a bridge within an opening of the substrate, the bridge attached to the first die and to the second die, wherein the bridge creates a connection between the first die and the second die, wherein the bridge has a first side, a second side, a third side and a fourth side from a plan view perspective, the plan view perspective parallel with the first side of the substrate, wherein the first die overlaps the first side and second side of the bridge but not the third side and fourth side of the bridge from the plan view perspective, and wherein the second die overlaps the second side and third side of the bridge but not the first side and fourth side of the bridge from the plan view perspective.