US 11,876,047 B2
Decoupled interconnect structures
Saumya Sharma, Easton, CT (US); Ashim Dutta, Clifton Park, NY (US); Tianji Zhou, Albany, NY (US); and Chih-Chao Yang, Glenmont, NY (US)
Assigned to International Business Machines Corporation, Armonk, NY (US)
Filed by International Business Machines Corporation, Armonk, NY (US)
Filed on Sep. 14, 2021, as Appl. No. 17/447,586.
Prior Publication US 2023/0081953 A1, Mar. 16, 2023
Int. Cl. H01L 21/00 (2006.01); H01L 23/528 (2006.01); H01L 21/768 (2006.01); H01L 23/522 (2006.01); H10B 61/00 (2023.01); H10B 63/00 (2023.01)
CPC H01L 23/528 (2013.01) [H01L 21/76816 (2013.01); H01L 21/76879 (2013.01); H01L 21/76843 (2013.01); H01L 23/5226 (2013.01); H10B 61/00 (2023.02); H10B 63/00 (2023.02)] 13 Claims
OG exemplary drawing
 
1. A semiconductor component, comprising:
an insulative layer having a lowermost surface arranged on top of a bottom dielectric material;
a first interconnect structure arranged in the bottom dielectric material such that an uppermost surface of the first interconnect structure is arranged at a first height relative to the lowermost surface of the insulative layer;
a device connected to the first interconnect structure and extending through the insulative layer; and
a second interconnect structure arranged such that a lowermost surface of the second interconnect structure is below the lowermost surface of the insulative layer and such that an uppermost surface of the second interconnect structure is arranged at a second height relative to the lowermost surface of the insulative layer, the second height different than the first height.