US 11,876,018 B2
Self-aligned trench MOSFET contacts having widths less than minimum lithography limits
Mitsuru Soma, Higashimatsuyama (JP); Masahiro Shimbo, Ojiya (JP); Masaki Kuramae, Aizuwakamatsu (JP); and Kouhei Uchida, Aizu-wakamatsu (JP)
Assigned to SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC, Scottsdale, AZ (US)
Filed by SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC, Phoenix, AZ (US)
Filed on Dec. 8, 2020, as Appl. No. 17/114,668.
Application 17/114,668 is a division of application No. 16/449,890, filed on Jun. 24, 2019, granted, now 10,892,188.
Claims priority of provisional application 62/860,959, filed on Jun. 13, 2019.
Prior Publication US 2021/0090953 A1, Mar. 25, 2021
Int. Cl. H01L 29/40 (2006.01); H01L 29/78 (2006.01); H01L 29/417 (2006.01); H01L 29/66 (2006.01); H01L 29/10 (2006.01); H01L 21/768 (2006.01); H01L 29/423 (2006.01); H01L 21/265 (2006.01); H01L 21/308 (2006.01); H01L 21/3213 (2006.01)
CPC H01L 21/76897 (2013.01) [H01L 21/26586 (2013.01); H01L 21/3086 (2013.01); H01L 21/32139 (2013.01); H01L 29/401 (2013.01); H01L 29/41741 (2013.01); H01L 29/4236 (2013.01); H01L 29/66666 (2013.01); H01L 29/7827 (2013.01); H01L 29/105 (2013.01); H01L 29/7813 (2013.01)] 11 Claims
OG exemplary drawing
 
1. A method of fabricating a semiconductor device on a substrate, comprising:
forming hard mask pillars on a surface of the substrate;
forming sacrificial spacers on a first side of each hard mask pillar and a second side of each hard mask pillar, wherein open gaps are formed between adjacent sacrificial spacers;
etching the hard mask pillars to form pillar gaps;
etching gate trenches into the substrate through the open gaps and the pillar gaps;
forming a gate electrode within the gate trenches;
implanting channels and sources in the substrate below the sacrificial spacers;
forming an insulator layer around the sacrificial spacers;
etching the sacrificial spacers to form contact trenches within the substrate; and
filling the contact trenches with a conductive material to form contacts.