US 11,876,013 B2
Gate dielectric preserving gate cut process
Shu-Yuan Ku, Hsinchu County (TW); Chih-Ming Sun, New Taipei (TW); and Chun-Fai Cheng, Tin Shui Wai (HK)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu (TW)
Filed on Oct. 14, 2021, as Appl. No. 17/501,818.
Application 16/709,291 is a division of application No. 15/963,297, filed on Apr. 26, 2018, granted, now 10,699,940, issued on Jun. 30, 2020.
Application 17/501,818 is a continuation of application No. 16/912,533, filed on Jun. 25, 2020, granted, now 11,152,250.
Application 16/912,533 is a continuation of application No. 16/709,291, filed on Dec. 10, 2019, granted, now 11,145,536, issued on Oct. 12, 2021.
Claims priority of provisional application 62/588,834, filed on Nov. 20, 2017.
Prior Publication US 2022/0037196 A1, Feb. 3, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 21/762 (2006.01); H01L 21/28 (2006.01); H01L 21/3213 (2006.01); H01L 21/8234 (2006.01); H01L 21/8238 (2006.01); H01L 27/088 (2006.01); H01L 29/78 (2006.01); H01L 29/66 (2006.01)
CPC H01L 21/76232 (2013.01) [H01L 21/32134 (2013.01); H01L 21/32135 (2013.01); H01L 21/32139 (2013.01); H01L 21/76224 (2013.01); H01L 21/823481 (2013.01); H01L 21/823821 (2013.01); H01L 21/823878 (2013.01); H01L 27/088 (2013.01); H01L 29/4011 (2019.08); H01L 29/785 (2013.01); H01L 21/823437 (2013.01); H01L 29/66795 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor device comprising:
a first gate stack and a second gate stack disposed in a first dielectric layer, wherein the first gate stack interposes first source/drain features and the second gate stack interposes second source/drain features along a first direction; and
a gate isolation structure disposed in the first dielectric layer, wherein the gate isolation structure interposes the first gate stack and the second gate stack along a second direction that is different than the first direction, and further wherein the gate isolation structure includes:
a first spacer and a second spacer abutting the first dielectric layer,
a second dielectric layer abutting the first spacer,
a third dielectric layer abutting the second spacer,
a fourth dielectric layer between the second dielectric layer and the third dielectric layer.