US 11,876,011 B2
3D semiconductor device and structure with single-crystal layers
Zvi Or-Bach, Haifa (IL); Brian Cronquist, Klamath Falls, OR (US); and Deepak C. Sekar, Sunnyvale, CA (US)
Assigned to Monolithic 3D Inc., Klamath Falls, OR (US)
Filed by Monolithic 3D Inc., Klamath Falls, OR (US)
Filed on Jun. 27, 2023, as Appl. No. 18/215,062.
Application 18/215,062 is a continuation in part of application No. 18/088,602, filed on Dec. 25, 2022, granted, now 11,735,462.
Application 18/088,602 is a continuation in part of application No. 17/855,775, filed on Jun. 30, 2022, granted, now 11,569,117, issued on Jan. 31, 2023.
Application 17/855,775 is a continuation in part of application No. 17/536,097, filed on Nov. 29, 2021, granted, now 11,521,888, issued on Dec. 6, 2022.
Application 17/536,097 is a continuation in part of application No. 17/140,130, filed on Jan. 3, 2021, granted, now 11,211,279, issued on Dec. 28, 2021.
Application 17/140,130 is a continuation in part of application No. 16/537,564, filed on Aug. 10, 2019.
Application 16/537,564 is a continuation in part of application No. 15/460,230, filed on Mar. 16, 2017, granted, now 10,497,713, issued on Dec. 3, 2019.
Application 15/460,230 is a continuation in part of application No. 14/821,683, filed on Aug. 7, 2015, granted, now 9,613,844, issued on Apr. 4, 2017.
Application 14/821,683 is a continuation in part of application No. 13/492,395, filed on Jun. 8, 2012, granted, now 9,136,153, issued on Sep. 15, 2015.
Application 13/492,395 is a continuation of application No. 13/273,712, filed on Oct. 14, 2011, granted, now 8,273,610, issued on Sep. 25, 2012.
Application 13/273,712 is a continuation in part of application No. 13/016,313, filed on Jan. 28, 2011, granted, now 8,362,482, issued on Jan. 29, 2013.
Application 13/016,313 is a continuation in part of application No. 12/970,602, filed on Dec. 16, 2010, granted, now 9,711,407, issued on Jul. 18, 2017.
Application 12/970,602 is a continuation in part of application No. 12/949,617, filed on Nov. 18, 2010, granted, now 8,754,533, issued on Jun. 17, 2014.
Prior Publication US 2023/0343632 A1, Oct. 26, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 27/02 (2006.01); H01L 27/06 (2006.01); H01L 27/092 (2006.01); H01L 27/10 (2006.01); H01L 27/105 (2023.01); H01L 27/118 (2006.01); H01L 27/12 (2006.01); H01L 29/423 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01); H01L 29/788 (2006.01); H01L 21/683 (2006.01); H01L 21/74 (2006.01); H01L 21/762 (2006.01); H01L 21/768 (2006.01); H01L 21/822 (2006.01); H01L 21/8238 (2006.01); H01L 21/84 (2006.01); H01L 23/48 (2006.01); H01L 23/525 (2006.01); H01L 29/792 (2006.01); G11C 8/16 (2006.01); H10B 10/00 (2023.01); H10B 12/00 (2023.01); H10B 20/00 (2023.01); H10B 41/20 (2023.01); H10B 41/40 (2023.01); H10B 41/41 (2023.01); H10B 43/20 (2023.01); H10B 43/40 (2023.01); H01L 23/367 (2006.01); H01L 25/065 (2023.01); H01L 25/00 (2006.01); H01L 23/00 (2006.01); H10B 20/20 (2023.01)
CPC H01L 21/6835 (2013.01) [G11C 8/16 (2013.01); H01L 21/743 (2013.01); H01L 21/76254 (2013.01); H01L 21/76898 (2013.01); H01L 21/8221 (2013.01); H01L 21/823828 (2013.01); H01L 21/84 (2013.01); H01L 23/481 (2013.01); H01L 23/5252 (2013.01); H01L 27/0207 (2013.01); H01L 27/0688 (2013.01); H01L 27/092 (2013.01); H01L 27/10 (2013.01); H01L 27/105 (2013.01); H01L 27/11807 (2013.01); H01L 27/11898 (2013.01); H01L 27/1203 (2013.01); H01L 29/4236 (2013.01); H01L 29/66272 (2013.01); H01L 29/66621 (2013.01); H01L 29/66825 (2013.01); H01L 29/66833 (2013.01); H01L 29/66901 (2013.01); H01L 29/78 (2013.01); H01L 29/7841 (2013.01); H01L 29/7843 (2013.01); H01L 29/7881 (2013.01); H01L 29/792 (2013.01); H10B 10/00 (2023.02); H10B 10/125 (2023.02); H10B 12/053 (2023.02); H10B 12/09 (2023.02); H10B 12/20 (2023.02); H10B 12/50 (2023.02); H10B 20/00 (2023.02); H10B 41/20 (2023.02); H10B 41/40 (2023.02); H10B 41/41 (2023.02); H10B 43/20 (2023.02); H10B 43/40 (2023.02); H01L 23/3677 (2013.01); H01L 24/13 (2013.01); H01L 24/16 (2013.01); H01L 24/45 (2013.01); H01L 24/48 (2013.01); H01L 25/0655 (2013.01); H01L 25/0657 (2013.01); H01L 25/50 (2013.01); H01L 27/1214 (2013.01); H01L 27/1266 (2013.01); H01L 2221/68368 (2013.01); H01L 2223/5442 (2013.01); H01L 2223/54426 (2013.01); H01L 2224/131 (2013.01); H01L 2224/16145 (2013.01); H01L 2224/16146 (2013.01); H01L 2224/16227 (2013.01); H01L 2224/16235 (2013.01); H01L 2224/32145 (2013.01); H01L 2224/32225 (2013.01); H01L 2224/45124 (2013.01); H01L 2224/45147 (2013.01); H01L 2224/48091 (2013.01); H01L 2224/48227 (2013.01); H01L 2224/73204 (2013.01); H01L 2224/73253 (2013.01); H01L 2224/73265 (2013.01); H01L 2224/81005 (2013.01); H01L 2224/83894 (2013.01); H01L 2225/06513 (2013.01); H01L 2225/06541 (2013.01); H01L 2924/00011 (2013.01); H01L 2924/01002 (2013.01); H01L 2924/01004 (2013.01); H01L 2924/01013 (2013.01); H01L 2924/01018 (2013.01); H01L 2924/01019 (2013.01); H01L 2924/01029 (2013.01); H01L 2924/01046 (2013.01); H01L 2924/01066 (2013.01); H01L 2924/01068 (2013.01); H01L 2924/01077 (2013.01); H01L 2924/01078 (2013.01); H01L 2924/01322 (2013.01); H01L 2924/10253 (2013.01); H01L 2924/10329 (2013.01); H01L 2924/12032 (2013.01); H01L 2924/12033 (2013.01); H01L 2924/12036 (2013.01); H01L 2924/12042 (2013.01); H01L 2924/1301 (2013.01); H01L 2924/1305 (2013.01); H01L 2924/13062 (2013.01); H01L 2924/13091 (2013.01); H01L 2924/14 (2013.01); H01L 2924/1461 (2013.01); H01L 2924/1579 (2013.01); H01L 2924/15311 (2013.01); H01L 2924/16152 (2013.01); H01L 2924/181 (2013.01); H01L 2924/19041 (2013.01); H01L 2924/3011 (2013.01); H01L 2924/3025 (2013.01); H01L 2924/30105 (2013.01); H10B 12/05 (2023.02); H10B 20/20 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A 3D semiconductor device, the device comprising:
a first level comprising a first single crystal layer, said first level comprising first transistors,
wherein each of said first transistors comprises a single crystal channel;
first metal layers interconnecting at least said first transistors;
a second metal layer overlaying said first metal layers;
a first oxide layer disposed over said second metal layer;
a second oxide layer disposed over said first oxide layer; and
a second level comprising a second single crystal layer, said second level comprising second transistors,
wherein said second level overlays said first level,
wherein at least one of said second transistors comprises a raised source or raised drain transistor structure,
wherein said second level is directly bonded to said first level, and
wherein said bonded comprises direct oxide-to-oxide bonds.