US 11,876,003 B2
Semiconductor package and packaging process for side-wall plating with a conductive film
Longnan Jin, Tianjin (CN); Heinrich Karrer, Regau (AT); Junfeng Liu, Tianjin (CN); Huiying Ding, Tianjin (CN); and Thomas Schmidt, Leonding (AT)
Assigned to VISHAY GENERAL SEMICONDUCTOR, LLC, Malvern, PA (US)
Filed by VISHAY GENERAL SEMICONDUCTOR, LLC, Malvern, PA (US)
Filed on Sep. 19, 2022, as Appl. No. 17/947,673.
Application 17/947,673 is a continuation of application No. 17/059,074, granted, now 11,450,534, previously published as PCT/US2020/017131, filed on Feb. 7, 2020.
Claims priority of application No. 201911347346.8 (CN), filed on Dec. 24, 2019.
Prior Publication US 2023/0019610 A1, Jan. 19, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 21/48 (2006.01); H01L 21/56 (2006.01); H01L 21/78 (2006.01); H01L 23/31 (2006.01); H01L 23/498 (2006.01); H01L 23/00 (2006.01)
CPC H01L 21/4842 (2013.01) [H01L 21/561 (2013.01); H01L 21/78 (2013.01); H01L 23/3107 (2013.01); H01L 23/49805 (2013.01); H01L 24/48 (2013.01); H01L 21/4839 (2013.01); H01L 2224/48245 (2013.01)] 17 Claims
OG exemplary drawing
 
1. A method for fabricating semiconductor packages from a package assembly comprising:
providing a lead frame assembly comprising a plurality of leads adjacently positioned, each lead comprising a first surface and a second surface;
encapsulating portions of the lead frame assembly in a mold encapsulation such that the second surface of each of the plurality of leads remain exposed, the mold encapsulation having a first major surface and a second major surface;
plating the second surface of each of the plurality of leads with a first electrical plating;
applying a conductive film across the second surface of each of the plurality of leads and the second major surface of the mold encapsulation;
cutting in a first direction through the mold encapsulation, each of the plurality of leads, and the first electrical plating on the second surface of each of the plurality of leads to create a channel in each of the plurality of leads, each of the channels exposing a first lead sidewall and a second lead sidewall of each of the plurality of leads;
plating, through the channel, the first lead sidewall and the second lead sidewall of each of the plurality of leads with a second electrical plating; and
removing the conductive film.