US 11,875,867 B2
Weighted wear leveling for improving uniformity
Zhongyuan Lu, Boise, ID (US); Karthik Sarpatwari, Boise, ID (US); and Nevil N. Gajera, Meridian, ID (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Dec. 8, 2021, as Appl. No. 17/545,335.
Prior Publication US 2023/0178167 A1, Jun. 8, 2023
Int. Cl. G11C 29/42 (2006.01); G11C 29/44 (2006.01); G11C 29/20 (2006.01); G11C 29/12 (2006.01)
CPC G11C 29/42 (2013.01) [G11C 29/1201 (2013.01); G11C 29/12005 (2013.01); G11C 29/20 (2013.01); G11C 29/4401 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A system comprising:
a memory device comprising a plurality of memory cells; and
a processing device operatively coupled with the memory device, to perform operations comprising:
grouping the plurality of memory cells into a plurality of groups based on a metric reflecting an electrical distance of a memory cell from a voltage source, wherein each group of the plurality of groups is defined by a respective maximum electrical distance and a respective minimum electrical distance from the voltage source to memory cells of the group;
determining, for each group of the plurality of groups, a respective share of write operations, wherein the share of write operations is related to an aggregate value of the metric for memory cells of the group; and
distributing the write operations to each group of the plurality of groups according to the share of write operations determined for the group.