US 11,875,860 B2
Intelligent charge pump architecture for flash array
Alberto Troia, Munich (DE); and Antonino Mondello, Messina (IT)
Filed by Lodestar Licensing Group LLC, Evanston, IL (US)
Filed on Jul. 21, 2022, as Appl. No. 17/870,714.
Application 17/870,714 is a continuation of application No. 16/624,879, granted, now 11,398,282, previously published as PCT/IB2019/000487, filed on May 31, 2019.
Prior Publication US 2022/0359019 A1, Nov. 10, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. G11C 16/30 (2006.01); G01R 31/3177 (2006.01); G11C 16/14 (2006.01); G11C 16/26 (2006.01); H02M 3/07 (2006.01)
CPC G11C 16/30 (2013.01) [G01R 31/3177 (2013.01); G11C 16/14 (2013.01); G11C 16/26 (2013.01); H02M 3/073 (2013.01); H02M 3/071 (2021.05)] 20 Claims
OG exemplary drawing
 
1. A memory device, comprising:
a plurality of sub-arrays;
a charge pump architecture, comprising:
a number of pump stages for increasing a value of an input voltage and obtaining an overvoltage output value to be provided to a selected one or more of the plurality of sub-arrays; and
a registers block comprising:
a pump address register indicating an address of the selected one or more of the plurality of sub-arrays; and
a number of registers storing values corresponding to respective target overvoltage characteristics, wherein the stored values correspond to a particular operation type to be performed on the selected one or more of the plurality of sub-arrays.