US 11,875,858 B2
Memory true erase with pulse steps to facilitate erase suspend
Tomoharu Tanaka, Yokohama (JP)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Feb. 1, 2022, as Appl. No. 17/590,742.
Claims priority of provisional application 63/231,059, filed on Aug. 9, 2021.
Prior Publication US 2023/0043066 A1, Feb. 9, 2023
Int. Cl. G11C 16/14 (2006.01); G11C 16/34 (2006.01); G11C 16/04 (2006.01); G06F 3/06 (2006.01); G11C 16/22 (2006.01)
CPC G11C 16/14 (2013.01) [G06F 3/0604 (2013.01); G06F 3/0652 (2013.01); G06F 3/0679 (2013.01); G11C 16/0483 (2013.01); G11C 16/225 (2013.01); G11C 16/3445 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A memory device comprising:
a memory array comprising memory cells; and
control logic operatively coupled to the memory array, the control logic to perform memory erase operations comprising:
performing a true erase sub-operation by causing multiple pulse steps to be applied sequentially to a group of memory cells of the memory array, wherein each sequential pulse step of the multiple pulse steps occurs during a pulse-step period and at a higher voltage compared to an immediately-preceding pulse-step;
in response to detecting an erase suspend command during a pulse step, suspending the true erase sub-operation at a start of a subsequent pulse-step period after the pulse step; and
resuming the true erase sub-operation at an end of the subsequent pulse-step period.