US 11,875,852 B2
Adaptive bias decoder to provide a voltage to a control gate line in an analog neural memory array in artificial neural network
Hieu Van Tran, San Jose, CA (US); Thuan Vu, San Jose, CA (US); Stanley Hong, San Jose, CA (US); Stephen Trinh, San Jose, CA (US); Anh Ly, San Jose, CA (US); Nhan Do, Saratoga, CA (US); and Mark Reiten, Alamo, CA (US)
Assigned to SILICON STORAGE TECHNOLOGY, INC., San Jose, CA (US)
Filed by Silicon Storage Technology, Inc., San Jose, CA (US)
Filed on Jan. 4, 2021, as Appl. No. 17/140,924.
Claims priority of provisional application 63/048,470, filed on Jul. 6, 2020.
Prior Publication US 2022/0004860 A1, Jan. 6, 2022
Int. Cl. G11C 7/12 (2006.01); G11C 16/08 (2006.01); G11C 11/54 (2006.01); G11C 16/24 (2006.01)
CPC G11C 16/08 (2013.01) [G11C 11/54 (2013.01); G11C 16/24 (2013.01); G11C 2216/04 (2013.01)] 14 Claims
OG exemplary drawing
 
1. A non-volatile memory system, comprising:
an array of non-volatile memory cells arranged in rows and columns, each non-volatile memory cell comprising a source and a drain;
a plurality of bit lines, each of the plurality of bit lines coupled to the drain of each non-volatile memory cell in a column of non-volatile memory cells;
a plurality of pull down bit lines, each of the plurality of pull down bit lines coupling a row of non-volatile memory cells to a reference node;
a source line coupled to the source of each non-volatile memory cell; and
an adaptive bias decoder to receive a row address and provide an adjusted voltage to a control gate line of a row in the array corresponding to the row address during an operation, wherein the adaptive bias decoder adjusts the adjusted voltage provided to the control gate line in response to a change in voltage of the reference node.