US 11,875,843 B2
Systems and methods for improved data access speed
Sanjeev Kumar Jain, Ottawa (CA)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Jan. 5, 2021, as Appl. No. 17/141,279.
Claims priority of provisional application 63/072,312, filed on Aug. 31, 2020.
Prior Publication US 2022/0068374 A1, Mar. 3, 2022
Int. Cl. G11C 11/419 (2006.01); G11C 11/418 (2006.01)
CPC G11C 11/419 (2013.01) [G11C 11/418 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A memory device, comprising:
a memory array;
a column selection circuit coupled to the memory array, wherein the column selection circuit is configured to generate a column selection signal;
a sense amplifier configured to receive data signals from the memory array; and
an enable signal generating circuit including a logic gate and an inverter having an input coupled to an output of the logic gate, wherein:
the logic gate is configured to receive an input enable signal at an input thereof and to generate a first enable signal at the output thereof;
the inverter is configured to generate a second enable signal at an output thereof;
the column selection circuit is coupled to the output of the logic gate and is configured to generate the column selection signal based on the first enable signal; and
the sense amplifier is configured to receive a data signal from the memory array in response to the first enable signal and the second enable signal.