CPC G11C 11/4096 (2013.01) [G11C 11/4074 (2013.01); G11C 11/4076 (2013.01); G11C 11/4085 (2013.01); G11C 11/4087 (2013.01)] | 14 Claims |
1. A method for optimizing an operation of a memory device, the method comprising the steps of:
accessing, by a first row decoder coupled to a first sub-block of a first memory block, the first sub-block of the first memory block at a first time; and
accessing, by a second row decoder separate from the first row decoder and coupled to a second sub-block of the first memory block, the second sub-block of the first memory block at a second time that is different from the first time,
wherein the second time defines a time delay that is chronologically after the first time, and
wherein the time delay is determined based upon a word line voltage ramp rate control.
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