US 11,875,842 B2
Systems and methods for staggering read operation of sub-blocks
Yu-Chung Lien, San Jose, CA (US); Deepanshu Dutta, Fremont, CA (US); and Tai-Yuan Tseng, Milpitas, CA (US)
Assigned to SANDISK TECHNOLOGIES LLC, Addison, TX (US)
Filed by SanDisk Technologies LLC, Addison, TX (US)
Filed on Nov. 9, 2021, as Appl. No. 17/522,414.
Prior Publication US 2023/0146549 A1, May 11, 2023
Int. Cl. G11C 7/12 (2006.01); G11C 11/4096 (2006.01); G11C 11/408 (2006.01); G11C 11/4074 (2006.01); G11C 11/4076 (2006.01)
CPC G11C 11/4096 (2013.01) [G11C 11/4074 (2013.01); G11C 11/4076 (2013.01); G11C 11/4085 (2013.01); G11C 11/4087 (2013.01)] 14 Claims
OG exemplary drawing
 
1. A method for optimizing an operation of a memory device, the method comprising the steps of:
accessing, by a first row decoder coupled to a first sub-block of a first memory block, the first sub-block of the first memory block at a first time; and
accessing, by a second row decoder separate from the first row decoder and coupled to a second sub-block of the first memory block, the second sub-block of the first memory block at a second time that is different from the first time,
wherein the second time defines a time delay that is chronologically after the first time, and
wherein the time delay is determined based upon a word line voltage ramp rate control.