US 11,875,727 B2
Shift register, gate driving circuit, display panel, and driving method thereof
Zhen Wang, Beijing (CN); Jian Zhang, Beijing (CN); Jian Sun, Beijing (CN); Wei Yan, Beijing (CN); Deshuai Wang, Beijing (CN); Wenwen Qin, Beijing (CN); Jiguo Wang, Beijing (CN); Han Zhang, Beijing (CN); Yue Shan, Beijing (CN); Xiaoyan Yang, Beijing (CN); Yadong Zhang, Beijing (CN); Shijun Wang, Beijing (CN); and Jiantao Liu, Beijing (CN)
Assigned to BOE TECHNOLOGY GROUP CO., LTD., Beijing (CN)
Appl. No. 17/593,953
Filed by BOE TECHNOLOGY GROUP CO., LTD., Beijing (CN)
PCT Filed Dec. 22, 2020, PCT No. PCT/CN2020/138322
§ 371(c)(1), (2) Date Sep. 28, 2021,
PCT Pub. No. WO2022/133729, PCT Pub. Date Jun. 30, 2022.
Prior Publication US 2022/0398968 A1, Dec. 15, 2022
Int. Cl. G09G 3/20 (2006.01); G09G 3/36 (2006.01); G11C 19/28 (2006.01)
CPC G09G 3/2096 (2013.01) [G09G 2310/0283 (2013.01); G09G 2310/0286 (2013.01); G09G 2310/08 (2013.01); G11C 19/28 (2013.01)] 17 Claims
OG exemplary drawing
 
1. A shift register, comprising:
an input circuit connected to an input signal terminal, an input control terminal, and a pull-up node of the shift register, wherein the input circuit is configured to input a potential of the input signal terminal to the pull-up node under the control of a signal of the input control terminal;
an output circuit connected to the pull-up node, a clock signal terminal, and an output signal terminal, wherein the output circuit is configured to provide a signal of the clock signal terminal to the output signal terminal under the control of a potential of the pull-up node;
a first control circuit connected to a first control signal terminal, the pull-up node, a pull-down node of the shift register, and a reference signal terminal, wherein the first control circuit is configured to provide a potential of the first control signal terminal to the pull-down node, and provide a potential of the reference signal terminal to the pull-down node according to the potential of the pull-up node;
a second control circuit connected to the pull-down node, a second control signal terminal, the output signal terminal, and the reference signal terminal, wherein the second control circuit is configured to pull down a potential of the output signal terminal in a display phase under the control of a potential of the pull-down node and a potential of the second control signal terminal, and pull up the potential of the output signal terminal in a power-off phase; and
a master reset circuit connected to a master reset signal terminal, the pull-up node, and the reference signal terminal,
wherein the second control circuit comprises:
a pull-down sub-circuit connected to the pull-down node, the output signal terminal, and the reference signal terminal, wherein the pull-down sub-circuit is configured to provide the potential of the reference signal terminal to the output signal terminal under the control of the potential of the pull-down node; and
a lower electronic circuit connected to the second control signal terminal, the pull-down node, the output signal terminal, and the reference signal terminal, wherein the lower electronic circuit is configured to, under the control of a signal of the second control signal terminal, provide the potential of the second control signal terminal to the output signal terminal and provide the potential of the reference signal terminal to the pull-down node,
wherein the pull-down sub-circuit comprises:
a third transistor having a gate electrode connected to the pull-down node, a first electrode connected to the reference signal terminal, and a second electrode connected to the output signal terminal;
a first capacitor having a first terminal connected to the pull-down node, and a second terminal connected to the reference signal terminal; and
a fourth transistor having a gate electrode connected to the output signal terminal, a first electrode connected to the reference signal terminal, and a second electrode connected to the pull-down node;
wherein:
in a power-on phase,
the master reset signal terminal is at a first level, the reference signal terminal is at a second level, the first level of the master reset signal terminal causes the master reset circuit to provide the second level of the reference signal terminal to the pull-up node, so as to reset the pull-up node; and
in the power-off phase,
the input control terminal is at a first level, the input signal terminal is at a second level, the reference signal terminal is at a second level, and the second control signal terminal is at a first level;
the first level of the input control terminal causes the input circuit to input the second level of the input signal terminal to the pull-up node;
the first level of the second control signal terminal causes the first transistor and the second transistor to be turned on, such that the first transistor provides the first level of the second control terminal to the output signal terminal, and the second transistor provides the second level of the reference signal terminal to the pull-down node; and
the first level of the output signal terminal causes the fourth transistor to be turned on, such that fourth transistor provides the second level of the reference signal terminal to the pull-down node, and the second level of the pull-down node causes the third transistor to be turned off.