US 11,875,453 B2
Decoupled shading pipeline
Karthik Vaidyanathan, Berkeley, CA (US); Marco Salvi, Seattle, WA (US); and Robert M. Toth, Lund (SE)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Apr. 5, 2021, as Appl. No. 17/222,347.
Application 17/222,347 is a continuation of application No. 16/984,729, filed on Aug. 4, 2020, granted, now 10,970,917.
Application 16/984,729 is a continuation of application No. 16/775,321, filed on Jan. 29, 2020, abandoned.
Application 16/775,321 is a continuation of application No. 15/398,111, filed on Jan. 4, 2017, granted, now 10,553,019, issued on Feb. 4, 2020.
Application 15/398,111 is a continuation of application No. 14/103,951, filed on Dec. 12, 2013, granted, now 9,569,883, issued on Feb. 14, 2017.
Prior Publication US 2021/0225066 A1, Jul. 22, 2021
This patent is subject to a terminal disclaimer.
Int. Cl. G06T 15/50 (2011.01); G06T 1/20 (2006.01)
CPC G06T 15/503 (2013.01) [G06T 1/20 (2013.01); G06T 2200/12 (2013.01)] 24 Claims
OG exemplary drawing
 
1. A system comprising:
a processor; and
a machine-readable storage storing instructions, the instructions executable by the processor to:
partition an image into at least a first region and a second region, wherein the first region is a peripheral region of the image;
prior to a display of the image on a display device, map a first render rate of a plurality of render rates to the peripheral region of the image;
prior to the display of the image on the display device, map a second render rate of the plurality of render rates to the second region of the image, wherein the second render rate is higher than the first render rate;
prior to the display of the image on the display device, perform rendering in the first region at the first render rate mapped to the peripheral region; and
prior to the display of the image on the display device, perform rendering in the second region at the second render rate mapped to the second region.