US 11,875,404 B2
Systems and methods for coordinating processing of scheduled instructions across multiple components
Zachary Bonig, Skokie, IL (US); Eric Thill, Naperville, IL (US); Pearce Peck-Walden, Chicago, IL (US); José Antonio Acuña-Rohter, Chicago, IL (US); Barry Galster, Chicago, IL (US); Neil Steuber, Evanston, IL (US); James Bailey, Hanover Park, IL (US); and Jake Siddall, Chicago, IL (US)
Assigned to Chicago Mercantile Exchange Inc., Chicago, IL (US)
Filed by Chicago Mercantile Exchange Inc., Chicago, IL (US)
Filed on Feb. 15, 2022, as Appl. No. 17/672,207.
Application 17/672,207 is a continuation of application No. 16/925,751, filed on Jul. 10, 2020, granted, now 11,288,744.
Application 16/925,751 is a continuation of application No. 15/232,208, filed on Aug. 9, 2016, granted, now 10,748,210, issued on Aug. 18, 2020.
Prior Publication US 2022/0172293 A1, Jun. 2, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. G06Q 40/04 (2012.01); G06Q 10/1093 (2023.01)
CPC G06Q 40/04 (2013.01) [G06Q 10/1093 (2013.01)] 23 Claims
OG exemplary drawing
 
1. A computer implemented method comprising:
receiving, at a same or different time by each of a plurality of processors coupled with a receiver, an augmented data message having been augmented upon receipt by the receiver with signal data which indicates that an instruction is to be processed by that processor, wherein each processor is coupled with a memory in which at least one instruction has been previously stored in association with data indicative of particular signal data; and
determining, by each of the plurality of processors, that the signal data of the received augmented data message, upon at least the commencement of processing thereof, corresponds with the particular signal data associated with one of the stored at least one instruction, and based thereon processing the corresponding one of the stored at least one instruction.