US 11,875,197 B2
Management of thrashing in a GPU
Bradford Michael Beckmann, Redmond, WA (US); Steven Tony Tye, Boxborough, MA (US); Brian L. Sumner, Bellevue, WA (US); and Nicolai Hähnle, Munich (DE)
Assigned to Advanced Micro Devices, Inc., Santa Clara, CA (US)
Filed by Advanced Micro Devices, Inc., Santa Clara, CA (US)
Filed on Dec. 29, 2020, as Appl. No. 17/136,738.
Prior Publication US 2022/0206876 A1, Jun. 30, 2022
Int. Cl. G06F 9/38 (2018.01); G06F 9/52 (2006.01); G06T 1/20 (2006.01); G06F 9/30 (2018.01)
CPC G06F 9/52 (2013.01) [G06F 9/30141 (2013.01); G06F 9/3836 (2013.01); G06T 1/20 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An apparatus comprising:
a register file comprising a plurality of registers;
a plurality of compute units comprising circuitry; and
a control unit comprising circuitry configured to:
allow a first number of wavefronts to execute concurrently on the plurality of compute units; and
allow no more than a second number of wavefronts to execute concurrently on the plurality of compute units, wherein the second number is less than the first number, in response to detection that thrashing of the register file is above a threshold.