US 11,875,183 B2
Real-time arbitration of shared resources in a multi-master communication and control system
Thomas Anton Leyrer, Geisenhausen (DE); and William Cronin Wallace, Richardson, TX (US)
Assigned to Texas Instruments Incorporated, Dallas, TX (US)
Filed by TEXAS INSTRUMENTS INCORPORATED, Dallas, TX (US)
Filed on May 29, 2019, as Appl. No. 16/424,667.
Claims priority of provisional application 62/677,878, filed on May 30, 2018.
Prior Publication US 2019/0370068 A1, Dec. 5, 2019
Int. Cl. G06F 9/48 (2006.01); G06F 16/9035 (2019.01); G06F 9/52 (2006.01); G06F 9/50 (2006.01); G06F 1/06 (2006.01); G06F 13/20 (2006.01); G06F 9/448 (2018.01); G06F 11/10 (2006.01); H04L 1/00 (2006.01); G06F 13/28 (2006.01); G06F 13/40 (2006.01)
CPC G06F 9/4881 (2013.01) [G06F 1/06 (2013.01); G06F 9/448 (2018.02); G06F 9/5011 (2013.01); G06F 9/5016 (2013.01); G06F 9/5038 (2013.01); G06F 9/52 (2013.01); G06F 11/1004 (2013.01); G06F 13/20 (2013.01); G06F 13/28 (2013.01); G06F 13/4068 (2013.01); G06F 16/9035 (2019.01); H04L 1/0041 (2013.01); G06F 2209/503 (2013.01); G06F 2209/5012 (2013.01)] 22 Claims
OG exemplary drawing
 
1. A circuit comprising:
an interconnect;
a first processor coupled to the interconnect by a first interface;
a second processor coupled to the interconnect by a second interface;
a computing resource coupled to the interconnect by a third interface;
an arbitration circuit coupled to the interconnect by a fourth interface, wherein the arbitration circuit is configured to maintain a plurality of flags, and a first flag of the plurality of flags is associated with the computing resource;
a broadside interface that is separate from the first interface, the second interface, the third interface, and the fourth interface and that is coupled to the arbitration circuit, the first processor, and the second processor, wherein:
the broadside interface includes a plurality of parallel interfaces including:
a fifth interface coupled between the first processor and the arbitration circuit; and
a sixth interface coupled between the second processor and the arbitration circuit;
the arbitration circuit includes a first logic circuit configured to:
in response to receiving a first instruction from the first processor and a second instruction from the second processor each requesting access to the computing resource, perform arbitration of the computing resource between the first processor and the second processor by assigning the computing resource to the first processor; and
set the first flag in response to assigning the computing resource; and
the arbitration circuit includes a second logic circuit configured to reset the first flag upon completion of an event associated with the computing resource; and
a task manager coupled to the second processor and configured to:
in response to determining that the computing resource is available, trigger processing by the second processor of a high priority task using the computing resource based on the first logic circuit granting the second processor access to the computing resource in response to the first flag being reset;
cause the second processor to execute a low priority task until the processing by the second processor of the high priority task is triggered; and
preempt processing of the low priority task by the second processor to process the high priority task in response to the processing by the second processor of the high priority task being triggered.