US 11,875,180 B2
Systems and methods for stalling host processor
Steven Milburn, Cranston, RI (US); and Gregory T. Sullivan, Rockport, MA (US)
Assigned to Dover Microsystems, Inc., Wayland, MA (US)
Filed by Dover Microsystems, Inc., Wayland, MA (US)
Filed on Aug. 3, 2022, as Appl. No. 17/880,539.
Application 17/880,539 is a continuation of application No. 17/308,868, filed on May 5, 2021, abandoned.
Application 17/308,868 is a continuation in part of application No. PCT/US2019/060028, filed on Nov. 6, 2019.
Application PCT/US2019/060028 is a continuation in part of application No. PCT/US2019/060030, filed on Nov. 6, 2019.
Claims priority of provisional application 62/756,465, filed on Nov. 6, 2018.
Prior Publication US 2023/0054942 A1, Feb. 23, 2023
Int. Cl. G06F 21/12 (2013.01); G06F 21/52 (2013.01); G06F 9/48 (2006.01); G06F 9/30 (2018.01); G06F 13/24 (2006.01); G06F 21/75 (2013.01)
CPC G06F 9/4812 (2013.01) [G06F 9/3013 (2013.01); G06F 9/30043 (2013.01); G06F 13/24 (2013.01); G06F 21/75 (2013.01)] 25 Claims
OG exemplary drawing
 
1. A method for stalling a host processor, the method comprising acts of:
causing the host processor to initiate one or more selected transactions, wherein:
the one or more selected transactions comprise a bus transaction; and
the act of causing the host processor to initiate one or more selected transactions comprises asserting an interrupt to cause the host processor to initiate the bus transaction, which comprises an operation with respect to a selected address; and
preventing the host processor from completing the one or more selected transactions, to thereby stall the host processor.