US 11,875,155 B2
Processing device with a microbranch target buffer for branch prediction using loop iteration count
Kai Chirca, Dallas, TX (US); Paul Daniel Gauvreau, Plano, TX (US); and David Edward Smith, Jr., Allen, TX (US)
Assigned to Texas Instruments Incorporated, Dallas, TX (US)
Filed by Texas Instruments Incorporated, Dallas, TX (US)
Filed on Jan. 19, 2022, as Appl. No. 17/578,516.
Application 17/578,516 is a continuation of application No. 16/888,783, filed on May 31, 2020, granted, now 11,294,681.
Claims priority of provisional application 62/855,468, filed on May 31, 2019.
Prior Publication US 2022/0137972 A1, May 5, 2022
Int. Cl. G06F 9/32 (2018.01); G06F 9/38 (2018.01)
CPC G06F 9/325 (2013.01) [G06F 9/3806 (2013.01); G06F 9/3846 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A processor comprising:
an instruction pipeline configured to process an instruction address; and
a branch predictor coupled to the instruction pipeline, the branch predictor configured to:
receive the instruction address;
determine a first status of the instruction address based on a first comparison of the instruction address with a first set of data;
in response to the first status of the instruction address corresponding to a hyperblock loop, determine a second status of the instruction address based on a second comparison of the instruction address with a second set of data;
in response to the second status of the instruction address indicating that the instruction address is included with the second set of data, determine a validity status of the second set of data associated with the instruction address; and
in response to the validity status being valid, predict, based on the second set of data associated with the instruction address, a number of iterations for a next occurrence of the hyperblock loop.