CPC G06F 9/325 (2013.01) [G06F 9/3806 (2013.01); G06F 9/3846 (2013.01)] | 20 Claims |
1. A processor comprising:
an instruction pipeline configured to process an instruction address; and
a branch predictor coupled to the instruction pipeline, the branch predictor configured to:
receive the instruction address;
determine a first status of the instruction address based on a first comparison of the instruction address with a first set of data;
in response to the first status of the instruction address corresponding to a hyperblock loop, determine a second status of the instruction address based on a second comparison of the instruction address with a second set of data;
in response to the second status of the instruction address indicating that the instruction address is included with the second set of data, determine a validity status of the second set of data associated with the instruction address; and
in response to the validity status being valid, predict, based on the second set of data associated with the instruction address, a number of iterations for a next occurrence of the hyperblock loop.
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