US 11,875,099 B2
Noise impact on function (NIOF) reduction for integrated circuit design
Gerald L Strevig, III, Cedar Park, TX (US); Adam P. Matheny, Hyde Park, NY (US); Alice Hwajin Lee, Belmont, MA (US); and Jose Luis Pontes Correia Neves, Poughkeepsie, NY (US)
Assigned to International Business Machines Corporation, New Armonk, NY (US)
Filed by International Business Machines Corporation, Armonk, NY (US)
Filed on Aug. 9, 2021, as Appl. No. 17/397,197.
Prior Publication US 2023/0038399 A1, Feb. 9, 2023
Int. Cl. G06F 30/327 (2020.01); G06F 30/394 (2020.01); G06F 119/10 (2020.01)
CPC G06F 30/327 (2020.01) [G06F 30/394 (2020.01); G06F 2119/10 (2020.01)] 20 Claims
OG exemplary drawing
 
1. A computer-implemented method comprising:
identifying, by a processing device, a first victim-aggressor pair of nets and a second first victim-aggressor pair of nets for an integrated circuit;
severing nets of the first victim-aggressor pair of nets and for the second victim-aggressor pair of nets to create a first severed segment between the first victim-aggressor pair of nets and a second severed segment between the second victim-aggressor pair of nets;
swapping the first severed segments of the first victim-aggressor pair of nets with the second severed segment of the second victim-aggressor pair of nets; and
rerouting the first victim-aggressor pair of nets and the second victim-aggressor pair of nets subsequent to the swapping.