US 11,875,063 B2
Memory system
Marie Takada, Yokohama (JP); Masanobu Shirakawa, Chigasaki (JP); and Tsukasa Tokutomi, Kamakura (JP)
Assigned to KIOXIA CORPORATION, Tokyo (JP)
Filed by KIOXIA CORPORATION, Tokyo (JP)
Filed on Dec. 16, 2022, as Appl. No. 18/082,759.
Application 18/082,759 is a continuation of application No. 17/370,535, filed on Jul. 8, 2021, granted, now 11,561,736.
Application 17/370,535 is a continuation of application No. 16/826,595, filed on Mar. 23, 2020, granted, now 11,086,573, issued on Aug. 10, 2021.
Application 16/826,595 is a continuation of application No. 16/118,543, filed on Aug. 31, 2018, granted, now 10,635,354, issued on Apr. 28, 2020.
Claims priority of application No. 2018-052646 (JP), filed on Mar. 20, 2018.
Prior Publication US 2023/0117717 A1, Apr. 20, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G11C 29/00 (2006.01); G06F 3/06 (2006.01); G11C 16/26 (2006.01); G11C 16/10 (2006.01); G11C 16/16 (2006.01); G11C 16/08 (2006.01); G06F 11/10 (2006.01); G11C 29/52 (2006.01); G11C 16/04 (2006.01); G11C 11/56 (2006.01); H10B 41/27 (2023.01); H10B 41/35 (2023.01); H10B 43/27 (2023.01); H10B 43/35 (2023.01)
CPC G06F 3/0659 (2013.01) [G06F 3/0604 (2013.01); G06F 3/0679 (2013.01); G06F 11/1068 (2013.01); G11C 16/0483 (2013.01); G11C 16/08 (2013.01); G11C 16/10 (2013.01); G11C 16/16 (2013.01); G11C 16/26 (2013.01); G11C 29/52 (2013.01); G11C 11/5621 (2013.01); G11C 11/5671 (2013.01); H10B 41/27 (2023.02); H10B 41/35 (2023.02); H10B 43/27 (2023.02); H10B 43/35 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A memory system, wherein the memory system comprises:
a memory controller;
a plurality of memory cells; and
a plurality of word lines, wherein
a first word line of the plurality of word lines is coupled to a first memory cell of the plurality of memory cells;
a second word line of the plurality of word lines is coupled to a second memory cell of the plurality of memory cells;
a third word line of the plurality of word lines is coupled to a third memory cell of the plurality of memory cells;
the memory controller is configured to:
send a first command in response to receiving a read command from a host; and
send a second command in response to determining a shift voltage of the first command exceeds a first threshold and does not exceed a second threshold; and
the memory system is configured to:
apply a first set of voltages to the first word line, the second word line, and the third word line in response to the first command; and
apply a second set of voltages, different from the first set of voltages, to the first word line, the second word line, and the third word line in response to the second command.