US 11,875,050 B2
Memory device
Hyung Jin Choi, Icheon-si (KR)
Assigned to SK hynix Inc., Icheon-si (KR)
Filed by SK hynix Inc., Icheon-si (KR)
Filed on Nov. 12, 2021, as Appl. No. 17/525,459.
Claims priority of application No. 10-2021-0007384 (KR), filed on Jan. 19, 2021.
Prior Publication US 2022/0229558 A1, Jul. 21, 2022
Int. Cl. G06F 3/00 (2006.01); G06F 3/06 (2006.01)
CPC G06F 3/064 (2013.01) [G06F 3/0604 (2013.01); G06F 3/0656 (2013.01); G06F 3/0679 (2013.01)] 19 Claims
OG exemplary drawing
 
1. A memory device comprising:
a memory block with memory cells to which word lines and bit lines are connected;
page buffers, connected to the memory block through the bit lines, during a program operation, configured to convert original data that is received from an external device into variable data with a plurality of data combinations that are divided into a plurality of groups according to a number of first level bits; and
a data pattern manager configured to control the page buffers to convert the original data into the variable data so that the number of the first level bits of data combinations included in each of the groups among the plurality of data combinations is the same during the program operation.