CPC G06F 3/0631 (2013.01) [G06F 3/0604 (2013.01); G06F 3/0673 (2013.01); G06F 13/28 (2013.01)] | 20 Claims |
1. An integrated circuit comprising:
an image processing circuit configured to perform an image processing operation on an input image that includes a first set of blocks of pixels to produce an output image that includes a second set of blocks of pixels;
a local memory; and
a scheduler coupled to the image processing circuit and to the local memory, wherein the scheduler is configured to:
determine a block size for the image processing operation;
determine whether to modify the block size based on an amount of available space in the local memory; and
cause the image processing circuit to perform the image processing operation on the input image to produce the output image.
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