CPC G06F 3/0626 (2013.01) [G06F 3/0658 (2013.01); G06F 3/0679 (2013.01); G06F 13/28 (2013.01); G06F 2213/28 (2013.01)] | 20 Claims |
1. A memory device, comprising:
an array of memory cells coupled to decoding and sensing circuitry, wherein a plurality of sub arrays of the array of memory cells is independently addressable inside the memory device;
sense amplifiers coupled to corresponding outputs of the plurality of sub-arrays and coupled to a communication channel; and
a scan chain including a plurality of Joint Test Action Group (JTAG) cells coupled in parallel between an output of the sense amplifiers and the communication channel, wherein the memory device is configured to fill the communication channel with an enlarged memory page including data, corresponding address bits, and ECC bits of each sub array of the plurality of sub arrays.
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