US 11,874,787 B2
Platform controller hub (PCH) chipsets in platforms as extended IO expander(s)
Amit K Srivastava, Folsom, CA (US); Majid Shushtarian, Pleasanton, CA (US); Anand K Enamandram, Folsom, CA (US); Jared W Havican, Folsom, CA (US); Jeffrey A Pihlman, Steilacoom, WA (US); Michael J Karas, Beaverton, OR (US); Ramamurthy Krithivas, Chandler, AZ (US); and Christine Watnik, Union City, CA (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Feb. 13, 2020, as Appl. No. 16/790,648.
Prior Publication US 2020/0183872 A1, Jun. 11, 2020
Int. Cl. G06F 13/40 (2006.01); G06F 9/4401 (2018.01)
CPC G06F 13/4063 (2013.01) [G06F 9/4403 (2013.01); G06F 9/4418 (2013.01)] 14 Claims
OG exemplary drawing
 
1. A method implemented on a platform including one or more central processing units (CPUs), a firmware storage device in which platform firmware is stored, and one or more controller hubs coupled to a platform control entity, each controller hub including a plurality of Input-Output (TO) interfaces and coupled to a respective CPU, each controller hub including at least one pin strap used to configure the controller hub to be implemented as a legacy controller hub or an IO-expander, the method comprising:
configurating at least one controller hub to be implemented as an IO expander under which the controller hub is used to expand the IO interfaces available to the CPU to which the controller hub is coupled; and
detecting a logic level at the at least one pin strap, and, in response thereto configuring the controller hub to be implemented as a legacy controller hub or an IO-expander.