US 11,874,779 B2
Scheduling of read operations and write operations based on a data bus mode
Wei Wang, Dublin, CA (US); Jiangli Zhu, San Jose, CA (US); Ying Yu Tai, Mountain View, CA (US); and Samir Mittal, Palo Alto, CA (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Dec. 4, 2020, as Appl. No. 17/112,748.
Application 17/112,748 is a continuation of application No. 16/132,875, filed on Sep. 17, 2018, granted, now 10,877,906.
Prior Publication US 2021/0089476 A1, Mar. 25, 2021
Int. Cl. G06F 13/16 (2006.01); G06F 3/06 (2006.01); G11C 7/10 (2006.01)
CPC G06F 13/1642 (2013.01) [G06F 3/061 (2013.01); G06F 3/0659 (2013.01); G06F 3/0671 (2013.01); G11C 7/1045 (2013.01); G06F 2213/16 (2013.01)] 12 Claims
OG exemplary drawing
 
1. A method, comprising:
determining that a data bus is in a write mode;
determining, by a processing device, whether a number of memory queues, among a plurality of memory queues, that identify at least one write operation satisfies a threshold criterion, wherein each of the plurality of memory queues is configured to include identifiers of one or more write operations and identifiers of one or more read operations, and wherein the determining of whether the number of memory queues that identify the at least one write operation satisfies the threshold criterion is responsive to an initial write operation not being identified at an available memory queue; and
responsive to determining that the number of memory queues satisfies the threshold criterion, transmitting a write operation from the plurality of memory queues over the data bus.