US 11,874,778 B2
Realm management unit-private memory regions
Jason Parker, Sheffield (GB); Matthew Lucien Evans, Cambridge (GB); Gareth Rhys Stockwell, Cambridge (GB); and Djordje Kovacevic, Cambridge (GB)
Assigned to Arm Limited, Cambridge (GB)
Appl. No. 16/625,943
Filed by ARM LIMITED, Cambridge (GB)
PCT Filed Jun. 11, 2018, PCT No. PCT/GB2018/051581
§ 371(c)(1), (2) Date Dec. 23, 2019,
PCT Pub. No. WO2019/002814, PCT Pub. Date Jan. 3, 2019.
Claims priority of application No. 1710345 (GB), filed on Jun. 28, 2017.
Prior Publication US 2020/0174950 A1, Jun. 4, 2020
Int. Cl. G06F 12/14 (2006.01); G06F 12/02 (2006.01); G06F 21/62 (2013.01)
CPC G06F 12/1458 (2013.01) [G06F 12/0253 (2013.01); G06F 21/6218 (2013.01); G06F 2212/1044 (2013.01)] 14 Claims
OG exemplary drawing
 
1. An apparatus comprising:
processing circuitry to perform data processing in response to one or more software processes;
memory access circuitry to enforce ownership rights for a plurality of memory regions, wherein a given memory region is owned by an owner realm specified from among a plurality of realms, each realm corresponding to at least a portion of at least one of the software processes, said owner realm having a right to exclude other realms from accessing data stored within said given memory region; and
realm management (RM) circuitry to perform realm management operations for managing said plurality of realms;
wherein the memory access circuitry is configured to control access to the given memory region in dependence on at least one status attribute specifying whether the given memory region is an RM-private memory region reserved for exclusive access by the realm management circuitry;
wherein the memory access circuitry is configured to prevent access to the given memory region by the owner realm for the given memory region when said given memory region is specified as said RM-private memory region by the at least one status attribute.