US 11,874,774 B2
Mechanism to efficiently rinse memory-side cache of dirty data
Ravindra N. Bhargava, Austin, TX (US); Ganesh Balakrishnan, Austin, TX (US); Joe Sargunaraj, Santa Clara, CA (US); Chintan S. Patel, Austin, TX (US); Girish Balaiah Aswathaiya, Austin, TX (US); and Vydhyanathan Kalyanasundharam, Santa Clara, CA (US)
Assigned to Advanced Micro Devices, Inc., Santa Clara, CA (US)
Filed by Advanced Micro Devices, Inc., Santa Clara, CA (US)
Filed on Sep. 24, 2020, as Appl. No. 17/031,834.
Prior Publication US 2022/0091991 A1, Mar. 24, 2022
Int. Cl. G06F 12/08 (2016.01); G06F 12/0891 (2016.01); G06F 9/46 (2006.01); G06F 12/0813 (2016.01); G06F 12/0831 (2016.01); G06F 12/084 (2016.01)
CPC G06F 12/0891 (2013.01) [G06F 9/467 (2013.01); G06F 12/084 (2013.01); G06F 12/0813 (2013.01); G06F 12/0833 (2013.01)] 22 Claims
OG exemplary drawing
 
1. A method, comprising:
in response to each read request of a plurality of read requests received at a memory-side cache device:
detecting an indication that cached data requested by the read request differs from backing data in a memory device coupled with the memory-side cache device when the read request causes a cache hit in the memory-side cache device;
in response to detecting the indication, performing a read rinse transaction by updating the backing data to match the cached data;
recording an indication that the cached data in the memory-side cache device matches the backing data in the memory device; and
in response to each write request of a plurality of write requests received at the memory-side cache device writing payload data specified by the write request to the memory-side cache device by storing the data in an entry of the memory-side cache device.