US 11,874,773 B2
Apparatuses, methods, and systems for dual spatial pattern prefetcher
Rahul Bera, Bangalore (IN); Anant Vithal Nori, Banglore (IN); and Sreenivas Subramoney, Bangalore (IN)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Dec. 28, 2019, as Appl. No. 16/729,344.
Claims priority of provisional application 62/903,550, filed on Sep. 20, 2019.
Prior Publication US 2021/0089456 A1, Mar. 25, 2021
Int. Cl. G06F 12/0862 (2016.01)
CPC G06F 12/0862 (2013.01) [G06F 2212/602 (2013.01)] 24 Claims
OG exemplary drawing
 
1. An apparatus comprising:
a processor core to access a memory and a cache that stores cache lines; and
a prefetch circuit to prefetch a cache line into the cache from the memory, wherein the prefetch circuit is to:
track page and cache line accesses to the cache for a single access signature,
generate a spatial bit pattern, for the cache line accesses for each page of a plurality of pages, that is shifted to a first cache line access for each page,
generate a single spatial bit pattern for the single access signature for each of the spatial bit patterns that have a same spatial bit pattern to form a plurality of single spatial bit patterns,
perform a logical OR operation on the plurality of single spatial bit patterns to create a first modulated bit pattern for the single access signature,
perform a logical AND operation on the plurality of single spatial bit patterns to create a second modulated bit pattern for the single access signature,
receive a prefetch request for the single access signature, and
perform a prefetch operation for the prefetch request using the first modulated bit pattern when a threshold is not exceeded and the second modulated bit pattern when the threshold is exceeded.