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1. A memory controller, comprising: an interface, configured to communicate with a plurality of memory cells organized in multiple Word Lines (WLs); and a processor configured to: read a Code Word (CW) of an Error Correction Code (ECC) from a group of multiple memory cells belonging to a target WL; calculate for a given memory cell in the group, (i) a first soft metric indicative of a first reliability level assigned to the given memory cell depending on a first threshold voltage of a first neighbor memory cell in a first WL neighboring the target WL, and (ii) a second soft metric indicative of a second reliability level assigned to the given memory cell depending on a second threshold voltage of a second neighbor memory cell in a second WL neighboring the target WL; calculate a combined soft metric based on both the first soft metric indicative of a first reliability level assigned to the given memory cell depending on a first threshold voltage of a first neighbor memory cell in a first WL neighboring the target WL and the second soft metric indicative of a second reliability level assigned to the given memory cell depending on a second threshold voltage of a second neighbor memory cell in a second WL neighboring the target WL, and assign the combined soft metric to the given memory cell; and decode the CW based at least on the combined soft metric, to produce a decoded CW.
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