US 11,874,325 B2
Integrated circuit, test assembly and method for testing an integrated circuit
Tobias Kilian, Munich (DE); Martin Huch, Munich (DE); Heiko Ahrens, Neubiberg (DE); and Daniel Tille, Unterhaching (DE)
Assigned to Infineon Technologies AG, Neubiberg (DE)
Filed by Infineon Technologies AG, Neubiberg (DE)
Filed on Sep. 14, 2022, as Appl. No. 17/944,239.
Claims priority of application No. 10 2021 123 889.7 (DE), filed on Sep. 15, 2021.
Prior Publication US 2023/0079599 A1, Mar. 16, 2023
Int. Cl. G01R 31/3185 (2006.01)
CPC G01R 31/318536 (2013.01) [G01R 31/31858 (2013.01); G01R 31/318541 (2013.01); G01R 31/318555 (2013.01); G01R 31/318583 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An integrated circuit, comprising:
a multiplicity of scan flip-flops;
a multiplicity of ring oscillator circuits, wherein each ring oscillator circuit comprises:
a chain of logic gates comprising a plurality of logic gates connected in succession;
an input multiplexer for the chain; and
a feedback line from an output connection of a last logic gate of the chain to a data input connection of the input multiplexer;
wherein each ring oscillator circuit is assigned a scan flip-flop group that contains at least one of the multiplicity of scan flip-flops, wherein the input multiplexer of the ring oscillator circuit is controlled depending on a control bit stored by the at least one of the multiplicity of scan flip-flops of the scan flip-flop group assigned to the ring oscillator circuit in such a way that the input multiplexer outputs an output bit fed back via the feedback line to a first logic gate of the chain when the control bit is in a first state and that the input multiplexer outputs an input bit that is to be processed by the first logic gate of the chain when the control bit is in a second state; and
wherein the ring oscillator circuits are assigned different scan flip-flop groups.