US 12,199,838 B2
Software-defined compute nodes on multi-SoC architectures
Guillaume Binet, Pittsburgh, PA (US); and Shailendra Deva, Saratoga, CA (US)
Assigned to Motional AD LLC, Boston, MA (US)
Filed by Motional AD LLC, Boston, MA (US)
Filed on Apr. 26, 2023, as Appl. No. 18/307,384.
Claims priority of provisional application 63/363,620, filed on Apr. 26, 2022.
Prior Publication US 2024/0089181 A1, Mar. 14, 2024
Int. Cl. H04L 41/40 (2022.01)
CPC H04L 41/40 (2022.05) 20 Claims
OG exemplary drawing
 
1. A computer-implemented method comprising:
obtaining a specification of a redundant node configuration for a multiprocessor-system-on-a-chip architecture, wherein the redundant node configuration specifies at least a first logical computing node implementing redundant operations using at least two multiprocessor-systems-on-a-chip, each of the at least two multiprocessor-systems-on-a-chip comprising multiple processors;
initializing, based on the specification of the redundant node configuration, communications between the at least two multiprocessor-systems-on-a-chip to form the redundant node configuration implementing redundant operations using the at least two multiprocessor-systems-on-a-chip; and
executing target computer-executable instructions on the redundant node configuration corresponding to the at least two multiprocessor-systems-on-a-chip in communication according to the specification of the redundant node configuration.