US 12,198,767 B2
Semiconductor memory device
Akio Sugahara, Yokohama Kanagawa (JP); Akihiro Imamoto, Kawasaki Kanagawa (JP); Toshifumi Watanabe, Yokohama Kanagawa (JP); Mami Kakoi, Yokohama Kanagawa (JP); Kohei Masuda, Yokohama Kanagawa (JP); Masahiro Yoshihara, Yokohama Kanagawa (JP); and Naofumi Abiko, Kawasaki Kanagawa (JP)
Assigned to Kioxia Corporation, Tokyo (JP)
Filed by Kioxia Corporation, Tokyo (JP)
Filed on Sep. 7, 2023, as Appl. No. 18/243,258.
Application 18/243,258 is a continuation of application No. 17/973,549, filed on Oct. 26, 2022, granted, now 11,783,899.
Application 17/973,549 is a continuation of application No. 17/200,996, filed on Mar. 15, 2021, granted, now 11,532,363, issued on Dec. 20, 2022.
Application 17/200,996 is a continuation of application No. PCT/JP2018/041195, filed on Nov. 6, 2018.
Prior Publication US 2023/0420054 A1, Dec. 28, 2023
Int. Cl. G11C 16/14 (2006.01); G11C 16/26 (2006.01); G11C 16/30 (2006.01); G11C 16/34 (2006.01)
CPC G11C 16/14 (2013.01) [G11C 16/26 (2013.01); G11C 16/30 (2013.01); G11C 16/3445 (2013.01)] 15 Claims
OG exemplary drawing
 
1. A semiconductor memory device comprising:
a first plane including a plurality of first blocks, each of the first blocks including a first memory cell:
a second plane including a plurality of second blocks, each of the second blocks including a second memory cell;
a voltage generator which includes a first driver configured to supply power to the first plane and a second driver configured to supply power to the second plane;
an input/output circuit configured to receive a command set from an external memory controller; and
a sequencer configured to execute an operation in response to the command set,
wherein:
upon receiving a first command set that instructs execution of a first operation to the first memory cell of one of the first blocks, the sequencer executes the first operation, the first operation causing a change of a threshold voltage of the first memory cell of the one of the first blocks,
upon receiving a second command set that instructs execution of a second operation to the second memory cell of one of the second blocks during execution of the first operation, the sequencer executes the second operation in parallel with the first operation, and
upon receiving a third command set that instructs execution of a third operation to the first memory cell of another one of the first blocks during execution of the first operation, the sequencer suspends the first operation, executes the third operation, and resumes the first operation upon completion of the third operation.