CPC H10N 50/80 (2023.02) [G11C 11/161 (2013.01); G11C 11/1673 (2013.01); G11C 11/1675 (2013.01); H10B 61/00 (2023.02); H10N 50/85 (2023.02)] | 20 Claims |
1. A magnetoelectric memory device, comprising:
a first electrode;
a second electrode;
a magnetic tunnel junction located between the first electrode and the second electrode, the magnetic tunnel junction comprising, from a side of the first electrode toward the second electrode, a first reference layer, a nonmagnetic tunnel barrier layer, a first nonmagnetic metal dust layer, a free layer, and a second nonmagnetic metal dust layer; and
a dielectric capping layer located between the magnetic tunnel junction and the second electrode,
wherein the first nonmagnetic metal dust layer and the second nonmagnetic metal dust layer have opposite signs of a voltage-controlled magnetic anisotropy coefficient.
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