US 11,871,596 B2
Display device and method of manufacturing the same
Jaybum Kim, Seoul (KR); Eoksu Kim, Seoul (KR); Kyoungseok Son, Seoul (KR); Junhyung Lim, Seoul (KR); and Jihun Lim, Hwaseong-si (KR)
Assigned to SAMSUNG DISPLAY CO., LTD., Yongin-si (KR)
Filed by SAMSUNG DISPLAY CO., LTD., Yongin-si (KR)
Filed on Oct. 28, 2020, as Appl. No. 17/082,379.
Application 17/082,379 is a continuation of application No. 16/911,525, filed on Jun. 25, 2020, granted, now 10,854,837.
Application 16/911,525 is a continuation of application No. 16/836,005, filed on Mar. 31, 2020, granted, now 10,790,467, issued on Sep. 29, 2020.
Application 16/836,005 is a continuation of application No. 16/459,060, filed on Jul. 1, 2019, granted, now 10,673,008, issued on Jun. 2, 2020.
Application 16/459,060 is a continuation of application No. 15/657,369, filed on Jul. 24, 2017, granted, now 10,340,472, issued on Jul. 2, 2019.
Claims priority of application No. 10-2016-0113445 (KR), filed on Sep. 2, 2016.
Prior Publication US 2021/0074943 A1, Mar. 11, 2021
This patent is subject to a terminal disclaimer.
Int. Cl. H10K 50/805 (2023.01); H10K 77/10 (2023.01); H10B 10/00 (2023.01); G09G 3/32 (2016.01); G09G 3/3233 (2016.01); H10K 59/121 (2023.01); H10K 71/00 (2023.01); H10K 50/30 (2023.01); H10K 59/12 (2023.01); H01L 51/52 (2006.01); H01L 51/00 (2006.01); H01L 27/11 (2006.01); H01L 27/32 (2006.01)
CPC H01L 51/5203 (2013.01) [G09G 3/32 (2013.01); G09G 3/3233 (2013.01); H01L 27/1108 (2013.01); H01L 27/3262 (2013.01); H01L 51/0096 (2013.01); G09G 2300/0426 (2013.01); G09G 2300/0814 (2013.01); G09G 2300/0842 (2013.01); G09G 2300/0861 (2013.01); G09G 2300/0866 (2013.01); G09G 2310/0245 (2013.01); G09G 2310/0262 (2013.01); H01L 27/3265 (2013.01); H01L 51/0023 (2013.01); H01L 51/5296 (2013.01); H01L 2227/323 (2013.01)] 19 Claims
OG exemplary drawing
 
1. A display device comprising:
a base substrate;
a first transistor above the base substrate and comprising a first semiconductor pattern below first, second, and third insulation layers and a first gate between the first insulation layer and the second insulation layer;
a second transistor above the base substrate and comprising a second gate between the first insulation layer and the second insulation layer, a second semiconductor pattern between the second insulation layer and the third insulation layer, and a third gate above the first, second, and third insulation layers and electrically connected to the second gate;
a third transistor above the base substrate and comprising a third semiconductor pattern below the first, second, and third insulation layers and a fourth gate between the first insulation layer and the second insulation layer;
a first conductive pattern on the first gate and overlapping the first gate;
at least one second conductive pattern on the third insulation layer; and
a light emitting diode above the third insulation layer,
wherein the third insulation layer is disposed between the first conductive pattern and the third gate,
the first semiconductor pattern comprises a polysilicon semiconductor and the second semiconductor pattern comprises an oxide semiconductor,
a first through hole is defined in the first, second, and third insulation layers to correspond to the first semiconductor pattern,
a second through hole is defined in the third insulation layer to correspond to the second semiconductor pattern, and
each of the first through hole and the second through hole is filled with a corresponding conductive pattern of the at least one second conductive pattern.