CPC H10B 53/20 (2023.02) [H01L 21/223 (2013.01); H01L 29/1037 (2013.01); H01L 29/66666 (2013.01); H01L 29/7827 (2013.01); H10B 51/20 (2023.02); H10B 51/30 (2023.02); H10B 53/30 (2023.02)] | 14 Claims |
1. A method of forming a vertical transistor comprising a top source/drain region, a bottom source/drain region, a channel region vertically between the top and bottom source/drain regions, and a gate operatively laterally-adjacent the channel region, the method comprising:
in multiple time-spaced microwave annealing steps, microwave annealing at least the channel region; the multiple time-spaced microwave annealing steps reducing average concentration of elemental-form H in the channel region from what it was before start of the multiple time-spaced microwave annealing steps, the reduced average concentration of elemental-form H being 0.005 to less than 1 atomic percent.
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