CPC H10B 43/40 (2023.02) [H01L 21/185 (2013.01); H01L 21/76898 (2013.01); H01L 24/80 (2013.01); H01L 25/0657 (2013.01); H01L 25/18 (2013.01); H10B 43/27 (2023.02); H10B 43/30 (2023.02); H10B 43/50 (2023.02); H01L 2224/08145 (2013.01)] | 15 Claims |
1. A semiconductor memory device comprising:
a semiconductor substrate;
a control circuit provided on the semiconductor substrate;
a solid state drive controller provided on the semiconductor substrate;
a first interconnection layer provided above the control circuit and the solid state drive controller;
a second interconnection layer provided above the first interconnection layer and including a plurality of bit lines; and
a three-dimensionally disposed plurality of memory cells above the plurality of bit lines and electrically connected to the control circuit through the first interconnection layer and the second interconnection layer, wherein
the control circuit is electrically connected to the solid state drive controller through the first interconnection layer,
a plurality of transistors consisting of the solid state drive controller are located on at least two areas of the semiconductor substrate, and
the control circuit includes at least one transistor disposed on an area between two areas among the at least two areas of the semiconductor substrate.
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