US 11,871,557 B2
Semiconductor device and semiconductor memory device
Taro Shiokawa, Nagoya Aichi (JP); Kiwamu Sakuma, Yokkaichi Mie (JP); and Keiko Sakuma, Yokkaichi Mie (JP)
Assigned to Kioxia Corporation, Tokyo (JP)
Filed by Kioxia Corporation, Tokyo (JP)
Filed on Mar. 9, 2022, as Appl. No. 17/690,425.
Claims priority of application No. 2021-153487 (JP), filed on Sep. 21, 2021.
Prior Publication US 2023/0088455 A1, Mar. 23, 2023
Int. Cl. H01L 27/108 (2006.01); H10B 12/00 (2023.01); H01L 29/786 (2006.01)
CPC H10B 12/30 (2023.02) [H01L 29/7869 (2013.01); H01L 29/78642 (2013.01)] 15 Claims
OG exemplary drawing
 
1. A semiconductor device comprising: a first electrode; a second electrode; an oxide semiconductor layer provided between the first electrode and the second electrode; a gate electrode opposed to the oxide semiconductor layer; a gate insulating layer provided between the oxide semiconductor layer and the gate electrode; a first insulating layer provided between the gate electrode and the first electrode; and a second insulating layer provided between the gate electrode and the second electrode, and the second insulating layer having an oxygen atom concentration lower than an oxygen atom concentration of the first insulating layer, and further comprising a substrate, the first electrode provided between the substrate and the second electrode.