CPC H04N 19/52 (2014.11) [H04N 19/109 (2014.11); H04N 19/139 (2014.11); H04N 19/176 (2014.11); H04N 19/577 (2014.11)] | 2 Claims |
1. An encoder comprising:
circuitry; and
memory coupled to the circuitry, wherein
in operation, the circuitry:
generates, in an inter prediction mode, a first prediction image of a current block to be processed, based on a derived motion vector; and
generates a final prediction image of the current block by applying an update process to the first prediction image,
candidates for the update process include a first process and a second process,
the first process is a bi-directional optical flow (BDOF) process,
the second process is a process of mixing the first prediction image with a second prediction image generated in intra prediction for the current block, and
in the applying of the update process, the first process and the second process are mutually exclusively applied.
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