CPC H04L 25/03057 (2013.01) [H03K 3/037 (2013.01); H03K 19/20 (2013.01)] | 20 Claims |
17. A summing circuit comprising a current summing circuit,
wherein the current summing circuit comprises:
a reference signal generator configured to generate a plurality of reference signals, based on a coefficient code;
a plurality of non-overlap clock buffers configured to generate a plurality of first switching signals and a plurality of second switching signals by using the plurality of reference signals, respectively; and
a plurality of current sources, each comprising a first switch, a second switch, and a current cell, and
wherein at least one of the first switch and the second switch of each of the plurality of current sources is in an off-state.
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