US 11,870,615 B2
Summing circuit and equalizer including the same
Kyeongjoon Ko, Yongin-si (KR); Jaehyun Park, Seoul (KR); Junhan Bae, Hwaseong-si (KR); Gyeongseok Song, Hwaseong-si (KR); and Jongjae Ryu, Changwon-si (KR)
Assigned to Samsung Electronics Co., Ltd., Gyeonggi-do (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on Jun. 8, 2022, as Appl. No. 17/835,373.
Claims priority of application No. 10-2021-0076250 (KR), filed on Jun. 11, 2021; and application No. 10-2021-0190391 (KR), filed on Dec. 28, 2021.
Prior Publication US 2022/0400036 A1, Dec. 15, 2022
Int. Cl. H04L 25/03 (2006.01); H03K 3/037 (2006.01); H03K 19/20 (2006.01)
CPC H04L 25/03057 (2013.01) [H03K 3/037 (2013.01); H03K 19/20 (2013.01)] 20 Claims
OG exemplary drawing
 
17. A summing circuit comprising a current summing circuit,
wherein the current summing circuit comprises:
a reference signal generator configured to generate a plurality of reference signals, based on a coefficient code;
a plurality of non-overlap clock buffers configured to generate a plurality of first switching signals and a plurality of second switching signals by using the plurality of reference signals, respectively; and
a plurality of current sources, each comprising a first switch, a second switch, and a current cell, and
wherein at least one of the first switch and the second switch of each of the plurality of current sources is in an off-state.