US 11,870,613 B2
Semiconductor integrated circuit and receiver device
Fumihiko Tachibana, Yokohama (JP)
Assigned to Kioxia Corporation, Tokyo (JP)
Filed by Kioxia Corporation, Tokyo (JP)
Filed on Jun. 16, 2022, as Appl. No. 17/807,265.
Claims priority of application No. 2022-023156 (JP), filed on Feb. 17, 2022.
Prior Publication US 2023/0261911 A1, Aug. 17, 2023
Int. Cl. H04L 25/03 (2006.01); H03L 7/08 (2006.01); H03L 7/089 (2006.01); H04L 25/49 (2006.01); H04L 7/00 (2006.01); H03M 1/12 (2006.01)
CPC H04L 25/03 (2013.01) [H03L 7/0807 (2013.01); H03L 7/089 (2013.01); H03M 1/12 (2013.01); H04L 7/0087 (2013.01); H04L 25/03057 (2013.01); H04L 25/4917 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor integrated circuit comprising:
a converter configured to convert an analog signal into a digital signal based on a clock signal;
a comparator configured to determine first data having data of a first number of bits per symbol and second data having data of a second number of bits, less than the first number, per symbol based on the digital signal;
a recovery circuit configured to recover the clock signal; and
a control circuit configured to input the digital signal and the first data to the recovery circuit in a case where a condition is not satisfied, and to input the digital signal and the second data to the recovery circuit in a case where the condition is satisfied.