US 11,870,404 B2
Gain stabilization
Kentaro Yamamoto, San Diego, CA (US); Aram Akhavan, San Diego, CA (US); Ganesh Kiran, San Diego, CA (US); Lei Sun, San Diego, CA (US); Elias Dagher, Laguna Niguel, CA (US); and Dinesh Jagannath Alladi, San Diego, CA (US)
Assigned to QUALCOMM Incorporated, San Diego, CA (US)
Filed by Qualcomm Incorporated, San Diego, CA (US)
Filed on May 13, 2021, as Appl. No. 17/320,077.
Prior Publication US 2022/0368299 A1, Nov. 17, 2022
Int. Cl. H03G 3/10 (2006.01); H03G 3/30 (2006.01); H03F 3/19 (2006.01); H03F 3/21 (2006.01); H03M 1/12 (2006.01)
CPC H03G 3/3036 (2013.01) [H03F 3/19 (2013.01); H03F 3/21 (2013.01); H03M 1/124 (2013.01); H03F 2200/453 (2013.01)] 30 Claims
OG exemplary drawing
 
1. An apparatus comprising:
a pipeline analog-to-digital converter comprising:
at least two stages; and
at least one amplification circuit coupled between the at least two stages, the at least one amplification circuit comprising:
an amplifier having a gain that is based on a bias voltage and an amplification control signal; and
a gain-stabilization circuit coupled to the amplifier, the gain-stabilization circuit comprising:
a replica amplifier corresponding to the amplifier, the replica amplifier configured to have a replica gain that is based on the bias voltage and the amplification control signal,
the gain-stabilization circuit configured to adjust at least one of the bias voltage or the amplification control signal based on a difference between an input voltage and an output voltage of the replica amplifier.